Conventionally, an injection-locked phase-locked loop (“IL-PLL”) has two steady-state reference phases. If there is a mismatch in such reference phases, then there may be a static-phase-offset (“SPO”). Such an SPO may result in large deterministic jitter. Furthermore, depending on what process-voltage-temperature (“PVT”) “corner” and/or variation may be “hit” by an injected pulse in an IL-PLL, one or more references spurs may be generated. These one or more reference spurs may cause jitter on an output clock from such IL-PLL. Along those lines, conventionally IL-PLLs have not been used in high-speed, low noise clock generation applications due to one or more such types of jitter.
Accordingly, it would be useful to provide an IL-PLL that overcomes one or more of the above-described limitations.